Synchronous memory devices can operate with data access latencies. A read latency can be the number of clock cycles between the application of a read instruction (and/or address) and the output of read data on the outputs of the memory device. Similarly, a write latency can be the number of clock cycles between the application of a write instruction (and/or address) and the application of write data at data inputs. With respect to write operations, there can also be a write data latency between the application of a write instruction/address (or write data), and the actual writing of the data into the memory array.
FIG. 17 shows a conventional synchronous memory device read path 1701. An address (ADD) can be applied to a memory array 1703 to access read data (data). Read data (data) is clocked through a number of clocked latches 1705-1, -2, -3 to an output register 1707. Each of the clocked latches (1705-1, -2, -3) can be controlled with a corresponding clock signal ck-lat1/2/3. To accommodate different latencies, different control circuits are designed to generate the clock signals (ck-lat1/2/3). The design of control circuits can be complicated and require simulation to ensure robust operation. While such a conventional approach can accommodate relatively shorter latencies (e.g., 1.0, 1.5, 2.0 and 2.5 clock cycles), such circuits may not accommodate larger latencies (e.g., 4 or more cycles).
FIG. 18 shows a conventional synchronous memory device write path 1801. Write data (D) can be applied to a series of latches 1805-0/1. A multiplexer (MUX) 1807-0 can selectively output write data (D) from either latch 1805-0/1 to vary a latency of data applied to a memory array. Variations in latency of an applied address (ADD) can be accomplished in the same manner, selecting address values from either latch 1805-2/3 with a MUX 1807-1.
FIG. 19 shows a conventional memory device clocked pipeline read path 1901. The read path 1901 can include memory array 1903, read data bus lines 1913, an error correction section 1909, a read data first-in-first-out circuit (FIFO) 1911, and timing registers 1907-1 to -3. Data transfers to each section occur by operation of a clock signal (clk) applied to the timing registers (1907-1 to -3). Read path 1901 is divided into four sections 1913-1 to -4. Each section (1913-1 to -4) should have equal delay. However, meeting such a delay requirement can be difficult to implement. Further, once such a clocked pipeline read path 1901 has been designed, it can be difficult to change between read latencies (e.g., from 4 cycles to 5 cycles) without incurring a speed penalty in device operations.